Aims

The aims of the course are to:

• provide fundamental knowledge and analytical skills required for VLSI systems design in the nanometre era
• illustrate the importance of custom design tools and also electronic design automation (EDA) for physical implementation, testing and verifications of VLSI systems

Objectives

As specific objectives, by the end of the course students should be able to:

• be familiar with the modern CMOS fabrication process, physical layout design rules and anticipate trends in VLSI fabrication technologies
• understand the trade-off between the four key design metrics of modern VLSI systems – cost, reliability, speed and power
• recognise the parasitic effect of wires/interconnects and apply wire delay models like lumped RC model and Elmore delay model
• understand the sources of power dissipation and the factors affecting robustness of a VLSI system
• design and optimise multi-level CMOS combinational and sequential circuits using static logic, pass transistor logic and dynamic logic
• operate up-to-date design tools for VLSI systems and evaluate the quality of the outputs (e.g. floorplan, placement, routing, verification, etc.)

Content

The module will introduce the design principles of integrated circuit designs with millions of digital devices. It begins with CMOS design flows and fabrication processes that creates modern VLSI and explains the design metrics (performance, power, cost, reliability). The typical combinational and sequential circuit design styles like static logic, pass transistor logic and dynmaic logic will be illustrated with many examples of digital devices. The effect of wires and interconnects on circuit speed and power will be studied. The module will be concluded with a case study of cutting-edge advanced VLSI technologies (e.g. FinFET) and design techniques.

Design Flow and Metrics (1L)

• Design flow: design, synthesis, planning, implementation, fabrication
• Cost: yield and detects of wafer die
• Reliability: noise margins, regenerative property of digital circuits
• Speed: delay definition, Fanout-of-four (FO4) delay
• Power: instantaneous, average, peak

CMOS Fabrication and Layout Design Rules (1L)

• Fabrication process: substrate preparation, photolithography, doping and diffusion, oxidation, packing
• Design rules: micron rules vs scalable rules, CMOS process layers, stick diagrams (sketch)

CMOS inverters and static gates (2L)

• CMOS I-V equations, velocity saturation in deep sub-micron devices
• Source and model of parasitic capacitances
• DC analysis of CMOS inverters
• Equivalent resistance model
• Logic gate design using switch model

Wires and Interconnects (1L)

• Interconnect parameters: capacitance, resistance and inductance
• Wire models: lumped model, lumped RC model, Elmore delay model
• Distributed RC line

High-speed Logic Design and Logical Effort (1L)

• Delay of logic gates
• Derivation of intrinsic delay and logic effort
• Optimisation for buffer sizing and the number of buffer stages
• Branching Effort

CMOS Sequential Circuit Design, Clocking (2L)

• Static latches, flip-flops, and registers
• Dynamic designs: C²MOS register and TSPC latch
• Clock tree and clocking strategies

Electronic Design Automation (EDA) tools for VLSI (1L)

• Synthesis: logic circuit modelling, timing models
• Placement: principles and challenges
• Routing: principles and challenges

Power and Robustness (1L)

• Dynamic power disspation
• Static comsumption
• Power analysis and optimisation technique
• Signal integrity issues

Packaging, I/O and Electrostatic Discharge Protection (1L)

• Common VLSI packaging options and issues
• Input and output (I/O) pad and buffer design
• Tri-state buffers

Advanced VLSI Technology and Design Techniques (e.g. FinFET, 3D stacking) (1L)

• Topics varies every year, suggestions from students are welcome.